Compilation Techniques for Reconfigurable Architectures

DOI10.1007/978-0-387-09671-1MaRDI QIDQ3521146zbMATH OpenOpenAlexFDO

Authors João M. P. Cardoso, Pedro C. Diniz

Publication date 28 August 2008

Full work available at URL https://doi.org/10.1007/978-0-387-09671-1

zbMATH Keywords

coarse-grained multicomputercomputation to architecture mappingfine-grained multicomputerFPGAreconfigurable architecture

Mathematics Subject Classification ID

Research exposition (monographs, survey articles) pertaining to computer science (68-02) Mathematical problems of computer architecture (68M07) Theory of compilers and interpreters (68N20)

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(9)

• Interprocedural compiler optimization for partial run-time reconfiguration
• Energy Efficient Hardware-Software Co-Synthesis Using Reconfigurable Hardware
• A pipelined-loop-compatible architecture and algorithm to reduce variable-length sets of floating-point data on a reconfigurable computer
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• scientific article; zbMATH DE number 1941139 (Why is no real title available?)
• scientific article; zbMATH DE number 1548492 (Why is no real title available?)
• scientific article; zbMATH DE number 2174302 (Why is no real title available?)
• Introduction to reconfigurable computing. Architectures, algorithms and applications. Foreword by Reiner Hartenstein.
• Languages and Compilers for Parallel Computing

Describes a project that uses

Uses Software

• Matlab

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