Compiler-directed dynamic frequency and voltage scheduling

DOI10.1007/3-540-44572-2_6MaRDI QIDQ2763245zbMATH OpenFDO

Authors Chung-hsing Hsu, Ulrich Kremer, Michael S. Hsiao

Publication date 14 January 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2008/20080065

Computing methodologies and applications (68U99)

Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies opportunities for dynamic voltage and frequency scaling of the CPU without significant increase in overall program execution time. The paper introduces a simple, yet effective performance model to determine an efficient CPU slow-down factor for memory bound loop computations. Simulation results of a superscalar target architecture and a program kernel compiled at different optimizations levels show the potential benefit of the proposed compiler optimization. The energy savings are reported for a hypothetical target machine with power dissipation characteristics similar to Transmeta's Crusoe TM5400 processor. For the entire collection see [Zbl 0976.68585].

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