DPA Leakage Models for CMOS Logic Circuits

DOI10.1007/11545262_27MaRDI QIDQ3522138zbMATH OpenOpenAlexFDO

Authors Daisuke Suzuki, M. Saeki, Tetsuya Ichikawa

Publication date 29 August 2008

Published in Cryptographic Hardware and Embedded Systems – CHES 2005 (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/11545262_27

Mathematics Subject Classification ID

Cryptography (94A60)

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Cited in

(11)

• Wavelet scattering transform and ensemble methods for side-channel analysis
• Monomial evaluation of polynomial functions protected by threshold implementations -- with an illustration on AES -- extended version
• Power analysis to ECC using differential power between multiplication and squaring
• Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
• Evolutionary ciphers against differential power analysis and differential fault analysis
• Practical Attacks on Masked Hardware
• Polar differential power attacks and evaluation
• A novel circuit design methodology to reduce side channel leakage
• Topics in Cryptology – CT-RSA 2005
• Secure hardware implementation of nonlinear functions in the presence of glitches
• Side-channel resistant crypto for less than 2,300 GE

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