Debugging VHDL designs using temporal process instances

DOI10.1007/3-540-45034-3_41MaRDI QIDQ4450892zbMATH OpenFDO

Authors Daniel Köb, Bernhard Peischl, Franz Wotawa

Publication date 16 February 2004

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2718/27180402.htm

zbMATH Keywords

debugging of hardware designsmodel-based diagnosissoftware debugging

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Theory of software (68N99) Computing methodologies and applications (68U99)

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Cited in

(4)

• Debugging hardware designs using a value-based model
• Model-based diagnosis of hardware designs
• Debugging VHDL designs: Introducing multiple models and first empirical results
• Using multiple models for debugging VHDL designs

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