Using multiple models for debugging VHDL designs

DOI10.1007/3-540-45517-5_16MaRDI QIDQ2772512zbMATH OpenFDO

Authors Franz Wotawa

Publication date 19 February 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2070/20700125

Mathematics Subject Classification ID

Theory of programming languages (68N15) Computing methodologies and applications (68U99)

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(4)

• Debugging hardware designs using a value-based model
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• Debugging VHDL designs: Introducing multiple models and first empirical results
• Debugging VHDL designs using temporal process instances

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