Delay-insensitive gate-level pipelining

DOI10.1016/S0167-9260(01)00013-XMaRDI QIDQ2778429zbMATH OpenOpenAlexFDO

Authors S. C. Smith, Ronald F. Demara, J. S. Yuan, M. Hagedorn, D. Ferguson

Publication date 3 March 2002

Published in Integration. The VLSI Journal (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0167-9260(01)00013-x

zbMATH Keywords

asynchronous logic designdual-rail encodingNULL convention logic (NCL)pipeliningself-timed circuits

Mathematics Subject Classification ID

Theory of computing (68Q99)

Recommendations

• scientific article; zbMATH DE number 1786641
• A formal approach to designing delay-insensitive circuits
• scientific article; zbMATH DE number 496062
• scientific article; zbMATH DE number 8785
• Asynchronous datapaths and the design of an asynchronous adder

Cited in

(4)

• A current sensing completion detection method for asynchronous pipelines operating in the sub‐threshold regime
• Practical delay enforced multistream (DEMUS) control of deeply pipelined processors
• Delay-insensitive pipelined communication on parallel buses
• scientific article; zbMATH DE number 1786641 (Why is no real title available?)

This page was built for publication: Delay-insensitive gate-level pipelining

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2778429)