Design of a pipelined radix 4 CORDIC processor

DOI10.1016/0167-8191(93)90061-OMaRDI QIDQ686627zbMATH OpenOpenAlexFDO

Authors E. L. Zapata, Javier D. Bruguera, Elisardo Antelo

Publication date 10 October 1993

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-8191(93)90061-o

zbMATH Keywords

CORDIC algorithmdigital signal processingpipeliningredundant arithmeticsigned-digit adders

Mathematics Subject Classification ID

Computer system organization (68M99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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(9)

• Pipelined CORDIC processors for generating Gaussian random numbers
• High-speed CORDIC based on an overlapped architecture and a novel \(\sigma\)-prediction method
• Numerical accuracy of Fast Fourier Transforms with CORDIC arithmetic
• Evaluation of CORDIC algorithms for FPGA design
• Unified mixed radix 2-4 redundant CORDIC processor
• The differential CORDIC algorithm: Constant scale factor redundant implementation without correcting iterations
• Householder CORDIC algorithms
• scientific article; zbMATH DE number 922639 (Why is no real title available?)
• Efficient CORDIC based implementation of selected signal processing algorithms

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