Efficient and High-Performance Parallel Hardware Architectures for the AES-GCM

DOI10.1109/TC.2011.125MaRDI QIDQ5274658zbMATH OpenOpenAlexFDO

Authors Mehran Mozaffari-Kermani, Arash Reyhani-Masoleh

Publication date 12 July 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2011.125

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Parallel algorithms in computer science (68W10) Cryptography (94A60)

Cited in

(3)

• A survey of some recent bit-parallel \(\mathrm{GF}(2^n)\) multipliers
• PSP: parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC
• Efficient Vector Implementations of AES-Based Designs: A Case Study and New Implemenations for Grøstl

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