Error-Resilient Low-Power Viterbi Decoder Architectures

DOI10.1109/TSP.2009.2026078MaRDI QIDQ4570024zbMATH OpenOpenAlexFDO

Authors Rami A. Abdallah, Naresh R. Shanbhag

Publication date 9 July 2018

Published in IEEE Transactions on Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tsp.2009.2026078

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Decoding (94B35)

Cited in

(4)

• VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements
• FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder
• scientific article; zbMATH DE number 6765480 (Why is no real title available?)
• An Approach for Adaptively Approximating the Viterbi Algorithm to Reduce Power Consumption While Decoding Convolutional Codes

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