Formal verification of digital circuits using symbolic ternary system models

DOI10.1007/BFB0023717MaRDI QIDQ4037372zbMATH OpenFDO

Authors Randal E. Bryant, Carl-Johan H. Seger

Publication date 18 May 1993

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/BFB0023717

zbMATH Keywords

Boolean expressionssequential circuitstemporal logic operatorsternary system modelingverifying synchronous digital circuits

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

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