Handling 16 instructions per cycle in a superscalar processor

DOI10.1016/S0167-739X(00)00053-4MaRDI QIDQ4538492zbMATH OpenFDO

Authors Bernard Goossens

Publication date 14 July 2002

Published in Future Generation Computer Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/S0167-739X(00)00053-4

zbMATH Keywords

superscalar degree 16 processor

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computer system organization (68M99)

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(6)

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• Euro-Par 2004 Parallel Processing

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