Performance scalability of multimedia instruction set extensions

DOI10.1007/3-540-45706-2_120MaRDI QIDQ4813165zbMATH OpenFDO

Authors D. Cheresiz, Ben H. H. Juurlink, Harry A. G. Wijshoff, Stamatis Vassiliadis

Publication date 12 August 2004

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2400/24000849.htm

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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• A cost-effective architecture for vectorizable numerical and multimedia applications
• Optimizing pipeline for a RISC processor with multimedia extension ISA
• Handling 16 instructions per cycle in a superscalar processor
• Measuring the performance of multimedia instruction sets
• Performance of the complex streamed instruction set on image processing kernels
• Memory bandwidth: The true bottleneck of SIMD multimedia performance on a superscalar processor

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