Easy test generation PLAs (Q1095867)

Test Generation for large circuits may be extremely difficult. One of the approaches to alleviating this problem is to consider the difficulties during the design cycle. This paper proposes a design of Easy Test Generation Programmable Logic Arrays (ETG PLAs), for which test generation is basically not required, since a complete test set can be generated while the test is applied. This paper also presents a procedure which makes a PLA an ETG PLA by following some design rules and providing reasonable extra hardware.