A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits (Q1339115)
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| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits |
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A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits (English)
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1 December 1994
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VLSI design
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logical test
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circuit partitioning
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graph partitioning
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integrated VLSI circuits
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tabu search
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