Neural Networks and Systolic Array Design (Q4779919)

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scientific article; zbMATH DE number 1821342
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    Neural Networks and Systolic Array Design
    scientific article; zbMATH DE number 1821342

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      Neural Networks and Systolic Array Design (English)
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      29 October 2002
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      Neural networks
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      Systolic array design
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      artificial neural networks
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      systolic array
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      parallel implementation
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      The book provides a collection of tutorial articles describing the basic concepts, characteristic features as well as recent developments and some of the significant applications of Systolic Array (SA) design for Artificial Neural Networks (ANN). Excepting the first chapter which is a tutorial introduction to ANN and SA concepts, all other fifteen chapters provide informations on reserches and rezults in some specific areas. In Chapter 2 a recursive linear neural network based on the Hopfield model has been introduced to solve the mixture problem. For the implementation the authors use SA. The proposed systolic structure is devided into two parts, one rectangular array for implementing the weight matrix and a linear array for computing the threshold vector. Both structures are used in the iterative process of NN and allow a reduction of computational cost. The application of SA to speed up the performance of an algorithm for unsupervised analysis of remote sensing images with high dimensionality is presented in Chapter 3. The proposed method is based on mathematical morphology. Chapter 4 devoted to the SA concept in neural computation focuses on the ANN machine architecture. There is a disscussion on the MANTRA I machine, GENES IV systolic array and the prototype SIMD computer with 400 processing elements expandable to 1600 processing elements. The performance of the machine is analyzed by using the Kohonen model. Design alternatives to digital or fully parallel analog implementations of neural fuzzy systems by means of mixed signal VLSI are discussed in Chapter 5. Chapter 6 focuses on systolic implementation for CMAC neural networks. An enhanced model, the higher order CMAC is introduced and a cost-efficient systolic array architecture to implement this with digital hardware is presented. The systolic CMAC architecture is then used to solve the color correction problem for a color reproduction environment. In Chapter 7 one shows the way Quadrant Interlocking Factorization procedure can be implemented on systolic and wavefront array processors. A SOM algorithm for hyperspectral classification implemented by a systolic array is presented in Chapter 8. Chapter 9 is devoted to the description of a method for optimizing the size of feedforward neural networks during the training process. The method is based on computing iteratively the optimum hidden nodes and on updating only the weights associated to these nodes. The optimizing and learning algorithm is implemented by a systolic architecture. Chapter 10 presents a system design methodology for fuzzy clustering networks. The mapping strategies from clustering neural network to system architecture and from the architecture to systolic arrays are discussed. In Chapter 11 a method for parallel time delay window computing is described. Two kinds of processing stages used in pipelined architectures together with the mapping strategies from the window computing model to systolic array structures are presented. Applications are done in speach recognition. Chapter 12 provides a review of different approaches to biosignal classification using adaptive logic networks, compare their performance and states conclusions regarding their applicability to biomedical engineering problems. The aim of Chapter 13 is to discuss optimal architectures for designing multiplierless multi-layer feedforward networks suitable for various combinations of discrete/continuous input to discrete/continuous output mappings. Chapter 14 describes a real time intelligent decision making system implementable in VLSI. The system architecture is an integration of an ANN and a fuzzy expert system. Chapter 15 focuses on a technical description of a large-scale evolvable hardware system for evolving compartmentally modeled neural circuits in silicon at high speed. The last chapter discusses the need of implementing ANNs on parallel architectures and presents two different methods for mapping the network model and its learning algorithm to the parallel architecture. The book is useful to graduate students and researchers in computer science, system science and electrical engineering. It has to be noticed the effort of editors to manage a unified, coherent and accurate presentation of the book.
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