Linear parametric model checking of timed automata
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Cites work
- A theory of timed automata
- Automata for modeling real-time systems
- Fun with fireWire: A comparative study of formal verification methods applied to the IEEE 1394 root contention protocol
- scientific article; zbMATH DE number 996442 (Why is no real title available?)
- Linear parametric model checking of timed automata
- Mechanical verification of the IEEE 1394a root contention protocol using Uppaal2k
- Parametric real-time reasoning
- Symbolic techniques for parametric reasoning about counter and clock systems
- TREX: A tool for reachability analysis of complex systems
- Uppaal in a nutshell
Cited in
(54)- Decision problems for lower/upper bound parametric timed automata
- TCTL model checking lower/upper-bound parametric timed automata without invariants
- On clock-aware LTL parameter synthesis of timed automata
- PTIME parametric verification of safety properties for reasonable linear hybrid automata
- Iterative bounded synthesis for efficient cycle detection in parametric timed automata
- Time based deadlock prevention for Petri nets
- Efficient convex zone merging in parametric timed automata
- On completeness of liveness synthesis for parametric timed automata (Extended Abstract)
- An extension of the inverse method to probabilistic timed automata
- Model checking of linear-time properties in multi-valued systems
- Consistency in parametric interval probabilistic timed automata
- Parametric multisingular hybrid Petri nets: formal definitions and analysis techniques
- Model measuring for discrete and hybrid systems
- Parameter synthesis for probabilistic timed automata using stochastic game abstractions
- Linear parametric model checking of timed automata
- Bounded Model Checking for Parametric Timed Automata
- Language preservation problems in parametric timed automata
- Model Checking Real-Time Systems
- Parametric Deadlock-Freeness Checking Timed Automata
- Parametric Timed Model Checking for Guaranteeing Timed Opacity
- Time Unbalanced Partial Order
- Parameter synthesis for probabilistic timed automata using stochastic game abstractions
- Robust Model-Checking of Linear-Time Properties in Timed Automata
- Linear Temporal Logic of Constraint Automata
- Robust synthesis for real-time systems
- LTL parameter synthesis of parametric timed automata
- Parity Automata for Quantitative Linear Time Logics
- Linear temporal logic symbolic model checking
- What's decidable about parametric timed automata?
- Parametric metric interval temporal logic
- Parameter synthesis for hierarchical concurrent real-time systems
- Parametric updates in parametric timed automata
- Parametric schedulability analysis of a launcher flight control system under reactivity constraints
- Cost problems for parametric time Petri nets
- scientific article; zbMATH DE number 7559425 (Why is no real title available?)
- Reachability and liveness in parametric timed automata
- Language preservation problems in parametric timed automata
- A game approach to the parametric control of real-time systems
- Parametric verification of weighted systems
- Decision Problems for Lower/Upper Bound Parametric Timed Automata
- Hierarchical reasoning for the verification of parametric systems
- On the Satisfiability and Model Checking for one Parameterized Extension of Linear-time Temporal Logic
- Distributed parametric model checking timed automata under non-zenoness assumption
- Parameter Synthesis for Bounded Cost Reachability in Time Petri Nets
- Parametric updates in parametric timed automata
- Repairing timed automata clock guards through abstraction and testing
- A rewriting-logic-with-SMT-based formal analysis and parameter synthesis framework for parametric time Petri nets
- Cycle encoding-based parameter synthesis for timed automata safety
- Dense integer-complete synthesis for bounded parametric timed automata
- Execution-time opacity problems in one-clock parametric timed automata
- Tweaking the odds in probabilistic timed automata
- Robust parametric reachability for timed automata
- Analysis of a biphase mark protocol with Uppaal and PVS
- Automatic generation of path conditions for concurrent timed systems
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