Massimo Alioto

List of research outcomes

This list is not complete and representing at the moment only items from zbMATH Open and arXiv. We are working on additional sources - please check back here soon!

Publication	Date of Publication	Type
Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read IEEE Transactions on Circuits and Systems I: Regular Papers	2021-09-02	Paper
Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of Variations IEEE Transactions on Circuits and Systems I: Regular Papers	2021-08-26	Paper
Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing IEEE Transactions on Circuits and Systems I: Regular Papers	2021-08-26	Paper
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial IEEE Transactions on Circuits and Systems I: Regular Papers	2021-08-26	Paper
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits IEEE Transactions on Circuits and Systems I: Regular Papers	2021-08-26	Paper
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the R&eacute;nyi Chaotic Map IEEE Transactions on Circuits and Systems I: Regular Papers	2017-11-20	Paper
A feedback strategy to improve the entropy of a chaos-based random bit generator IEEE Transactions on Circuits and Systems I: Regular Papers	2017-11-20	Paper
Modeling and Evaluation of Positive-Feedback Source-Coupled Logic IEEE Transactions on Circuits and Systems I: Regular Papers	2017-10-04	Paper
A simple strategy for optimized design of one-level carry-skip adders IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications	2017-08-25	Paper
Simple and accurate modeling of the output transition time in nanometer CMOS gates International Journal of Circuit Theory and Applications	2011-02-17	Paper
Modelling and design considerations on CML gates under high-current effects International Journal of Circuit Theory and Applications	2006-02-21	Paper
Power-delay optimization of D-latch/MUX source coupled logic gates International Journal of Circuit Theory and Applications	2005-03-08	Paper
An efficient implementation of PRNGs based on the digital sawtooth map International Journal of Circuit Theory and Applications	2005-01-12	Paper
Modelling of source-coupled logic gates International Journal of Circuit Theory and Applications	2002-09-25	Paper

Research outcomes over time

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