Minimizing energy on homogeneous processors with shared memory
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This paper considers the system-wide energy-efficient task scheduling problem in a system architecture equipped with a multi-core processor and a shared main memory. The focus is on the case when the number of tasks is greater than the number of cores, which has been proved to be NP-hard if the number of cores is at least 2. For the multiple-cores case, based on observation from the single-core case, a polynomial-time approximation algorithm is devised with guaranteed performance.
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Cites work
- A fully polynomial-time approximation scheme for speed scaling with a sleep state
- Algorithms for dynamic speed scaling
- Algorithms for power savings
- An O(n^2) algorithm for computing optimal continuous voltage schedules
- Energy-efficient scheduling and routing via randomized rounding
- Flow shop for dual CPUs in dynamic voltage scaling
- scientific article; zbMATH DE number 1306870 (Why is no real title available?)
- Low complexity scheduling algorithms minimizing the energy for tasks with agreeable deadlines
- Minimizing energy on homogeneous processors with shared memory
- On multi-processor speed scaling with migration
- Polynomial-time algorithms for minimum energy scheduling
- Race to idle or not: balancing the memory sleep time with DVS for energy minimization
- Scheduling to minimize gaps and power consumption
- Scheduling unit tasks to minimize the number of idle periods
- Speed scaling on parallel processors
- Speed scaling on parallel processors with migration
- Speed scaling problems with memory/cache consideration
Cited in
(8)- Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling
- A Monte Carlo algorithm for real time task scheduling on multi-core processors with software controlled dynamic voltage scaling
- Race to idle or not: balancing the memory sleep time with DVS for energy minimization
- Thermal implications of energy-saving schedulers
- Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP
- Multi-Processor Computer System Having Low Power Consumption
- Minimizing energy on homogeneous processors with shared memory
- Multi-core processor scheduling with respect to data bus bandwidth
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