Multi-core processor scheduling with respect to data bus bandwidth

DOI10.1007/978-3-030-65739-0_5arXiv2010.16058OpenAlexW3184581504MaRDI QIDQ6130872

Maria Y. Sosnovskaya, Anton Valentinovich Eremeev, Maxim A. Sakhno, Anton A. Malakhov

Publication date: 3 April 2024

Published in: Communications in Computer and Information Science (Search for Journal in Brave)

Full work available at URL: https://arxiv.org/abs/2010.16058

zbMATH Keywords

schedulinggreedy algorithmmixed integer linear programmingmulti-core processordata bus

Mathematics Subject Classification ID

Mixed integer programming (90C11) Deterministic scheduling theory in operations research (90B35) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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