Modeling and simulation of efficient March algorithm for memory testing

DOI10.1007/978-3-642-14825-5_9MaRDI QIDQ3058899zbMATH OpenOpenAlexFDO

Authors Balwinder Singh, Sukhleen Bindra Narang, Arun Khosla

Publication date 7 December 2010

Published in Communications in Computer and Information Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-14825-5_9

zbMATH Keywords

VLSI testingMarch algorithmsmemory built in self-test

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Recommendations

• scientific article; zbMATH DE number 2172010
• Analysis of multibackground memory testing techniques
• The repeated nondestructive march tests with variable address sequences
• Theory of transparent BIST for RAMs
• BIST for systems-on-a-chip

Cited in

(3)

• scientific article; zbMATH DE number 2172010 (Why is no real title available?)
• Analysis of multibackground memory testing techniques
• Infrastructure intellectual property for SoC simulation and diagnosis service

This page was built for publication: Modeling and simulation of efficient March algorithm for memory testing

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3058899)