Modular exponentiation on fine-grained FPGA

DOI10.1007/3-540-45353-9_17MaRDI QIDQ2724442zbMATH OpenFDO

Authors Alexander A. Tiountchik, Elena Trichina

Publication date 10 July 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/3-540-45353-9_17

zbMATH Keywords

bit-level systolic algorithmfield programmable gate arraysmodular exponentiationMontgomery multiplication

Mathematics Subject Classification ID

Cryptography (94A60)

Recommendations

• RSA acceleration with field programmable gate arrays
• Compact modular exponentiation accelerator for modern FPGA devices
• A modular exponentiation unit based on systolic arrays
• Bit-level systolic array for fast exponentiation in GF(2/sup m/)
• scientific article; zbMATH DE number 5041007

Cited in

(3)

• Compact modular exponentiation accelerator for modern FPGA devices
• RSA acceleration with field programmable gate arrays
• A high performance ROM-based structure for modular exponentiation

This page was built for publication: Modular exponentiation on fine-grained FPGA

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2724442)