Multidimensional DSP core synthesis for FPGA

DOI10.1007/S11265-006-7271-5MaRDI QIDQ2432185zbMATH OpenOpenAlexFDO

Authors Yanyan Li

Publication date 25 October 2006

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s11265-006-7271-5

zbMATH Keywords

field programmable gate arrayheterogeneous systemdataflow grapharchitectural synthesisrapid implementationsystem level design.

Mathematics Subject Classification ID

Computer system organization (68M99)

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Cites work

• scientific article; zbMATH DE number 918595 (Why is no real title available?)
• Compilation from Matlab to process networks realized in FPGA
• High speed FPGA-based implementations of delayed-LMS filters
• How rapid is rapid prototyping? Analysis of ESPADON programme results

Cited in

(7)

• A compact DSP core with static floating-point arithmetic
• scientific article; zbMATH DE number 1941143 (Why is no real title available?)
• scientific article; zbMATH DE number 1844661 (Why is no real title available?)
• scientific article; zbMATH DE number 1751894 (Why is no real title available?)
• scientific article; zbMATH DE number 918592 (Why is no real title available?)
• Multidimensional exploration of software implementations for DSP algorithms
• AVSynDEx: a rapid prototyping process dedicated to the implementation of digital image processing applications on multi-DSP and FPGA architectures

Describes a project that uses

Uses Software

• Xilinx
• ESPADON

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