Parallel Parsing Algorithms and VLSI Implementations for Syntactic Pattern Recognition

DOI10.1109/TPAMI.1984.4767522MaRDI QIDQ3311705zbMATH OpenWikidataFDO

Authors

Publication date 1984

Published in IEEE Transactions on Pattern Analysis and Machine Intelligence (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TPAMI.1984.4767522

zbMATH Keywords

Earley's algorithmerror-correcting recognitionparallel CFL parsingparallel CFL recognitionparsing matrixsyntactic pattern recognitionVLSI array

Mathematics Subject Classification ID

Theory of compilers and interpreters (68N20) Theory of operating systems (68N25) Pattern recognition, speech recognition (68T10)

Cited in

(11)

• Algorithm partition and parallel recognition of general context-free languages using fixed-size VLSI architecture
• VLSI architectures for string matching and pattern matching
• Efficient simulations of simple models of parallel computation by time- bounded ATMs and space-bounded TMs
• A parallel parsing algorithm for arbitrary context-free grammars
• Efficient reconfigurable embedded parsers
• Efficient error-correcting parsing for (attributed and stochastic) tree grammars
• parallel parsing from recurrence equations
• An NC algorithm for recognizing tree adjoining languages
• Systolic parsing of context-free languages
• An efficient all-parses systolic algorithm for general context-free parsing
• Parallel \(LL\) parsing

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