Shuvra S. Bhattacharyya

Available identifiers

Publication	Date of Publication	Type
PRUNE: Dynamic and Decidable Dataflow for Signal Processing on Heterogeneous Platforms	2019-02-12	Paper
A Wideband Front-End Receiver Implementation on GPUs	2019-02-07	Paper
Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation	2018-06-12	Paper
Contention-conscious transaction ordering in multiprocessor DSP systems	2017-10-30	Paper
The hierarchical timing pair model for multirate DSP applications	2017-09-20	Paper
Parameterized dataflow modeling for DSP systems	2017-09-08	Paper
Analysis of dataflow programs with interval-limited data-rates	2006-10-25	Paper
High-level synthesis of DSP applications using adaptive negative cycle detection	2005-05-03	Paper
Logic foundry: Rapid prototyping for FPGA-based DSP systems	2004-11-19	Paper
https://portal.mardi4nfdi.de/entity/Q4471675	2004-07-30	Paper
Intermediate representations for design automation of multiprocessor DSP systems	2003-02-17	Paper
https://portal.mardi4nfdi.de/entity/Q4790576	2003-02-04	Paper
Resynchronization for multiprocessor DSP systems	2002-03-25	Paper
Multidimensional exploration of software implementations for DSP algorithms	2000-05-07	Paper
https://portal.mardi4nfdi.de/entity/Q4888827	1996-08-21	Paper
Generating compact code from dataflow specifications of multirate signal processing algorithms	1995-06-21	Paper

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