| Publication | Date of Publication | Type |
|---|
Subcube allocation in hypercube computers
IEEE Transactions on Computers | 2018-09-14 | Paper |
A fault-tolerant communication scheme for hypercube computers
IEEE Transactions on Computers | 2018-09-14 | Paper |
Design, analysis and test of logic circuits under uncertainty
Lecture Notes in Electrical Engineering | 2012-06-15 | Paper |
| Quantum Circuit Simulation | 2009-11-26 | Paper |
Optimal synthesis of linear reversible circuits
(available as arXiv preprint) | 2008-11-03 | Paper |
Graph-based simulation of quantum computation in the density matrix representation
(available as arXiv preprint) | 2008-09-03 | Paper |
Improving gate-level simulation of quantum circuits
Quantum Information Processing | 2005-11-07 | Paper |
A local-sparing design methodology for fault-tolerant multiprocessors
Computers & Mathematics with Applications | 1998-06-11 | Paper |
| scientific article; zbMATH DE number 913340 (Why is no real title available?) | 1996-12-09 | Paper |
| scientific article; zbMATH DE number 861431 (Why is no real title available?) | 1996-09-29 | Paper |
| scientific article; zbMATH DE number 913359 (Why is no real title available?) | 1996-08-05 | Paper |
| scientific article; zbMATH DE number 913541 (Why is no real title available?) | 1996-08-05 | Paper |
Testability of convergent tree circuits
IEEE Transactions on Computers | 1996-01-01 | Paper |
Edge fault tolerance in graphs
Networks | 1993-09-05 | Paper |
Design of gracefully degradable hypercube-connected systems
Journal of Parallel and Distributed Computing | 1993-01-17 | Paper |
Designing fault-tolerant systems using automorphisms
Journal of Parallel and Distributed Computing | 1992-06-26 | Paper |
On meshy trees
International Journal of Computer Mathematics | 1989-01-01 | Paper |
A survey of the theory of hypercube graphs
Computers & Mathematics with Applications | 1988-01-01 | Paper |
Fault recovery in distributed processing loop networks
Computer Networks and ISDN Systems | 1988-01-01 | Paper |
Pseudo-Boolean Logic Circuits
IEEE Transactions on Computers | 1986-01-01 | Paper |
An Array Layout Methodology for VLSI Circuits
IEEE Transactions on Computers | 1986-01-01 | Paper |
Fault-tolerance and performance analysis of beta-networks
Parallel Computing | 1986-01-01 | Paper |
Uncertainty, Energy, and Multiple-Valued Logics
IEEE Transactions on Computers | 1986-01-01 | Paper |
Fault-Tolerance of Dynamic-Full-Access Interconnection Networks
IEEE Transactions on Computers | 1984-01-01 | Paper |
Testing Memories for Single-Cell Pattern-Sensitive Faults
IEEE Transactions on Computers | 1980-01-01 | Paper |
Design of Totally Fault Locatable Combinational Networks
IEEE Transactions on Computers | 1980-01-01 | Paper |
Identification of Equivalent Faults in Logic Networks
IEEE Transactions on Computers | 1980-01-01 | Paper |
| scientific article; zbMATH DE number 3597833 (Why is no real title available?) | 1978-01-01 | Paper |
| scientific article; zbMATH DE number 3627070 (Why is no real title available?) | 1978-01-01 | Paper |
Generation of Optimal Transition Count Tests
IEEE Transactions on Computers | 1978-01-01 | Paper |
Path Complexity of Logic Networks
IEEE Transactions on Computers | 1978-01-01 | Paper |
A Graph Model for Fault-Tolerant Computing Systems
IEEE Transactions on Computers | 1976-01-01 | Paper |
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers | 1976-01-01 | Paper |
Enumeration of Fanout-Free Boolean Functions
Journal of the ACM | 1976-01-01 | Paper |
On the Properties of Irredundant Logic Networks
IEEE Transactions on Computers | 1976-01-01 | Paper |
The Fanout Structure of Switching Functions
Journal of the ACM | 1975-01-01 | Paper |
Detection oF Pattern-Sensitive Faults in Random-Access Memories
IEEE Transactions on Computers | 1975-01-01 | Paper |
Test Point Placement to Simplify Fault Detection
IEEE Transactions on Computers | 1974-01-01 | Paper |
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests
IEEE Transactions on Computers | 1971-01-01 | Paper |
A Nand Model ror Fault Diagnosis in Combinational Logic Networks
IEEE Transactions on Computers | 1971-01-01 | Paper |
