John P. Hayes

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Person:427732

Available identifiers

zbMath Open hayes.john-pMaRDI QIDQ427732

List of research outcomes

PublicationDate of PublicationType
A fault-tolerant communication scheme for hypercube computers2018-09-14Paper
Subcube allocation in hypercube computers2018-09-14Paper
Design, analysis and test of logic circuits under uncertainty2012-06-15Paper
Quantum Circuit Simulation2009-11-26Paper
https://portal.mardi4nfdi.de/entity/Q35346182008-11-03Paper
https://portal.mardi4nfdi.de/entity/Q35225142008-09-03Paper
Improving gate-level simulation of quantum circuits2005-11-07Paper
A local-sparing design methodology for fault-tolerant multiprocessors1998-06-11Paper
https://portal.mardi4nfdi.de/entity/Q48877301996-12-09Paper
https://portal.mardi4nfdi.de/entity/Q48711651996-09-29Paper
https://portal.mardi4nfdi.de/entity/Q48877521996-08-05Paper
https://portal.mardi4nfdi.de/entity/Q48878121996-08-05Paper
Testability of convergent tree circuits1996-01-01Paper
Edge fault tolerance in graphs1993-09-05Paper
Design of gracefully degradable hypercube-connected systems1993-01-17Paper
Designing fault-tolerant systems using automorphisms1992-06-26Paper
On meshy trees1989-01-01Paper
A survey of the theory of hypercube graphs1988-01-01Paper
Fault recovery in distributed processing loop networks1988-01-01Paper
Fault-tolerance and performance analysis of beta-networks1986-01-01Paper
Uncertainty, Energy, and Multiple-Valued Logics1986-01-01Paper
Pseudo-Boolean Logic Circuits1986-01-01Paper
An Array Layout Methodology for VLSI Circuits1986-01-01Paper
Fault-Tolerance of Dynamic-Full-Access Interconnection Networks1984-01-01Paper
Design of Totally Fault Locatable Combinational Networks1980-01-01Paper
Testing Memories for Single-Cell Pattern-Sensitive Faults1980-01-01Paper
Identification of Equivalent Faults in Logic Networks1980-01-01Paper
Generation of Optimal Transition Count Tests1978-01-01Paper
Path Complexity of Logic Networks1978-01-01Paper
https://portal.mardi4nfdi.de/entity/Q41647761978-01-01Paper
https://portal.mardi4nfdi.de/entity/Q41891971978-01-01Paper
Transition Count Testing of Combinational Logic Circuits1976-01-01Paper
A Graph Model for Fault-Tolerant Computing Systems1976-01-01Paper
On the Properties of Irredundant Logic Networks1976-01-01Paper
Enumeration of Fanout-Free Boolean Functions1976-01-01Paper
Detection oF Pattern-Sensitive Faults in Random-Access Memories1975-01-01Paper
The Fanout Structure of Switching Functions1975-01-01Paper
Test Point Placement to Simplify Fault Detection1974-01-01Paper
A Nand Model ror Fault Diagnosis in Combinational Logic Networks1971-01-01Paper
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests1971-01-01Paper

Research outcomes over time


Doctoral students

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