| Publication | Date of Publication | Type |
|---|
| Subcube allocation in hypercube computers | 2018-09-14 | Paper |
| A fault-tolerant communication scheme for hypercube computers | 2018-09-14 | Paper |
| Design, analysis and test of logic circuits under uncertainty | 2012-06-15 | Paper |
| Quantum Circuit Simulation | 2009-11-26 | Paper |
| https://portal.mardi4nfdi.de/entity/Q3534618 | 2008-11-03 | Paper |
| Graph-based simulation of quantum computation in the density matrix representation | 2008-09-03 | Paper |
| Improving gate-level simulation of quantum circuits | 2005-11-07 | Paper |
| A local-sparing design methodology for fault-tolerant multiprocessors | 1998-06-11 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4887730 | 1996-12-09 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4871165 | 1996-09-29 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4887752 | 1996-08-05 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4887812 | 1996-08-05 | Paper |
| Testability of convergent tree circuits | 1996-01-01 | Paper |
| Edge fault tolerance in graphs | 1993-09-05 | Paper |
| Design of gracefully degradable hypercube-connected systems | 1993-01-17 | Paper |
| Designing fault-tolerant systems using automorphisms | 1992-06-26 | Paper |
| On meshy trees | 1989-01-01 | Paper |
| A survey of the theory of hypercube graphs | 1988-01-01 | Paper |
| Fault recovery in distributed processing loop networks | 1988-01-01 | Paper |
| Pseudo-Boolean Logic Circuits | 1986-01-01 | Paper |
| An Array Layout Methodology for VLSI Circuits | 1986-01-01 | Paper |
| Fault-tolerance and performance analysis of beta-networks | 1986-01-01 | Paper |
| Uncertainty, Energy, and Multiple-Valued Logics | 1986-01-01 | Paper |
| Fault-Tolerance of Dynamic-Full-Access Interconnection Networks | 1984-01-01 | Paper |
| Testing Memories for Single-Cell Pattern-Sensitive Faults | 1980-01-01 | Paper |
| Design of Totally Fault Locatable Combinational Networks | 1980-01-01 | Paper |
| Identification of Equivalent Faults in Logic Networks | 1980-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4164776 | 1978-01-01 | Paper |
| Generation of Optimal Transition Count Tests | 1978-01-01 | Paper |
| Path Complexity of Logic Networks | 1978-01-01 | Paper |
| https://portal.mardi4nfdi.de/entity/Q4189197 | 1978-01-01 | Paper |
| A Graph Model for Fault-Tolerant Computing Systems | 1976-01-01 | Paper |
| Transition Count Testing of Combinational Logic Circuits | 1976-01-01 | Paper |
| Enumeration of Fanout-Free Boolean Functions | 1976-01-01 | Paper |
| On the Properties of Irredundant Logic Networks | 1976-01-01 | Paper |
| The Fanout Structure of Switching Functions | 1975-01-01 | Paper |
| Detection oF Pattern-Sensitive Faults in Random-Access Memories | 1975-01-01 | Paper |
| Test Point Placement to Simplify Fault Detection | 1974-01-01 | Paper |
| On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests | 1971-01-01 | Paper |
| A Nand Model ror Fault Diagnosis in Combinational Logic Networks | 1971-01-01 | Paper |
