Design, analysis and test of logic circuits under uncertainty

DOI10.1007/978-90-481-9644-9MaRDI QIDQ427733zbMATH OpenOpenAlexFDO

Authors Smita Krishnaswamy, Igor L. Markov, John P. Hayes

Publication date 15 June 2012

Published in Lecture Notes in Electrical Engineering (Search for Journal in Brave)

Full work available at URL http://hdl.handle.net/2027.42/61584

zbMATH Keywords

combinational logic circuitprobabilistic faultprobabilistic fault testprobabilistic transfer matrixreliable circuit designsignature-based reliability analysissoft error

Mathematics Subject Classification ID

Research exposition (monographs, survey articles) pertaining to information and communication theory (94-02) Fault detection; testing in circuits and networks (94C12)

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• A Circuit Model for Fault Tolerance in the Reliable Assembly of Nano-systems
• Approximate reasoning about logic circuits with single-fan-out unreliable gates
• Signature rollback with extreme compaction -- a technique for testing robust VLSI circuits with reduced hardware overhead
• Flexible reliability assessment of digital circuits based on signal probability
• On the susceptibility of QDI circuits to transient faults
• Output-signal processing algorithms in statistical checking of logic circuits
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• From variability tolerance to approximate computing in parallel integrated architectures and accelerators
• Methods of testability analysis for digital logic
• Modelling reliability of reversible circuits with 2D second-order cellular automata

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Uses Software

• CPLEX

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