Design, analysis and test of logic circuits under uncertainty
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Publication:427733
DOI10.1007/978-90-481-9644-9zbMath1259.94003OpenAlexW1604782092MaRDI QIDQ427733
Igor L. Markov, Smita Krishnaswamy, John P. Hayes
Publication date: 15 June 2012
Published in: Lecture Notes in Electrical Engineering (Search for Journal in Brave)
Full work available at URL: http://hdl.handle.net/2027.42/61584
combinational logic circuitprobabilistic faultprobabilistic fault testprobabilistic transfer matrixreliable circuit designsignature-based reliability analysissoft error
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