Design, analysis and test of logic circuits under uncertainty
DOI10.1007/978-90-481-9644-9zbMATH Open1259.94003OpenAlexW1604782092MaRDI QIDQ427733FDOQ427733
Authors: Smita Krishnaswamy, Igor L. Markov, John P. Hayes 
Publication date: 15 June 2012
Published in: Lecture Notes in Electrical Engineering (Search for Journal in Brave)
Full work available at URL: http://hdl.handle.net/2027.42/61584
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combinational logic circuitprobabilistic faultprobabilistic fault testprobabilistic transfer matrixreliable circuit designsignature-based reliability analysissoft error
Research exposition (monographs, survey articles) pertaining to information and communication theory (94-02) Fault detection; testing in circuits and networks (94C12)
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- Flexible reliability assessment of digital circuits based on signal probability
- NBTI-aware transient fault rate analysis method for logic circuit based on probability voltage transfer characteristics
- A state-of-the-art current mirror-based reliable wide fan-in FinFET domino OR gate design
- Exact reliability analysis of combinational logic circuits
- From variability tolerance to approximate computing in parallel integrated architectures and accelerators
- Approximate reasoning about logic circuits with single-fan-out unreliable gates
- Yield analysis of partial defect tolerant bit-plane array
- Output-signal processing algorithms in statistical checking of logic circuits
- The development of technology-independent metrics for evaluation of the masking properties of logic
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- Accurate reliability analysis method for quantum-dot cellular automata circuits
- On the susceptibility of QDI circuits to transient faults
- Methods of testability analysis for digital logic
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- Modelling reliability of reversible circuits with 2D second-order cellular automata
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