A Circuit Model for Fault Tolerance in the Reliable Assembly of Nano-systems

DOI10.1007/978-3-540-89985-3_86zbMATH Open1188.68078OpenAlexW284298418MaRDI QIDQ3628404FDOQ3628404

Authors: Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi 

Publication date: 20 May 2009

Published in: Communications in Computer and Information Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-89985-3_86

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zbMATH Keywords

bifurcationcircuit modelfault-tolerancenanotechnologymultiplexing

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cites Work

• Title not available (Why is that?)
• On the maximum tolerable noise for reliable computation by formulas

Cited In (3)

• Tropical algebra based framework for error propagation analysis in systolic arrays
• Defect-tolerance in cellular nanocomputers
• FAULT-TOLERANT NANOCOMPUTERS BASED ON ASYNCHRONOUS CELLULAR AUTOMATA

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