Practical formal methods for hardware design

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This book is a collection of papers about the use of formal methods in the design and verification process of computer hardware. All contributions arise from the FORMAT project, a project that has been supported by the EU between 1992 and 1995. The goal of this project was to push the use of formal methods in industrial practice by providing and developing adequate languages, approaches and tools to support a formal verification and synthesis process. The papers are grouped into three parts. The first part consists of papers that describe and overview the languages, tools and design and verification flows developed by the FORMAT project. Part II is dedicated to the industrial experience. Several practical design projects making use of these formal methods are reviewed. Part III contains the more technical body of the FORMAT project. It presents in several papers the formalisms, algorithms and tools, which haved been used to support formal verification and synthesis from formal specifications.











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