Processor architectures for multimedia applications

DOI10.1007/3-540-45874-3_11MaRDI QIDQ4471692zbMATH OpenFDO

Authors Peter Pirsch, Arne Freimann, C. Klar, Jens Peter Wittenburg

Publication date 30 July 2004

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2268/22680188.htm

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computing methodologies and applications (68U99)

Recommendations

• Architecture concepts for multimedia signal processing
• scientific article; zbMATH DE number 1862258
• Reconfigurable media processing
• Reconfigurable coprocessor for multimedia application domain
• scientific article; zbMATH DE number 2090671

Cited in

(13)

• DSPs for image and video processing.
• Architecture concepts for multimedia signal processing
• Reconfigurable media processing
• Architecture of an image rendering Co-processor for MPEG-4 visual compositing
• Scalable architecture for soC video encoders
• Reconfigurable coprocessor for multimedia application domain
• Low-power high-performance adaptive computing architectures for multimedia processing
• A 2D addressing mode for multimedia applications
• A two dimensional vector architecture for multimedia
• scientific article; zbMATH DE number 1862258 (Why is no real title available?)
• scientific article; zbMATH DE number 2090671 (Why is no real title available?)
• Exploring hypermedia processor design space
• Multimedia execution hardware accelerator

This page was built for publication: Processor architectures for multimedia applications

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4471692)