Low-power high-performance adaptive computing architectures for multimedia processing

DOI10.1007/3-540-36265-7_12MaRDI QIDQ4417449zbMATH OpenFDO

Authors Rama Sangireddy, Huesung Kim, Arun K. Somani

Publication date 29 July 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2552/25520124.htm

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Recommendations

• A run-time reconfigurable cache architecture
• Architecture concepts for multimedia signal processing
• Processor architectures for multimedia applications
• Reconfigurable media processing
• Reconfigurable coprocessor for multimedia application domain

This page was built for publication: Low-power high-performance adaptive computing architectures for multimedia processing

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4417449)