Reconfigurable coprocessor for multimedia application domain

DOI10.1007/S11265-006-7512-7MaRDI QIDQ2505088zbMATH OpenOpenAlexFDO

Authors Salvatore M. Carta, Danilo Pani, Luigi Raffo

Publication date 29 September 2006

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s11265-006-7512-7

zbMATH Keywords

multimediareconfigurable computingdigital signal processingdomain-specific architectures

Mathematics Subject Classification ID

Learning and adaptive systems in artificial intelligence (68T05) Circuits, networks (94C99) Digital control/observation systems (93C62)

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Cites work

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Cited in

(9)

• scientific article; zbMATH DE number 2079656 (Why is no real title available?)
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• Embedding of dedicated high-performance ASICs into reconfigurable systems providing additional multimedia functionality
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Describes a project that uses

Uses Software

• MediaBench

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