Pseudo-vectorization and RISC optimization techniques for the Hitachi SR8000 architecture

DOI10.1007/978-3-642-55526-8_34MaRDI QIDQ4429610zbMATH OpenOpenAlexFDO

Authors Georg Hager, Frank Deserno, Gerhard Wellein

Publication date 26 September 2003

Published in High Performance Computing in Science and Engineering, Munich 2002 (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-55526-8_34

zbMATH Keywords

performancevector supercomputers

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

Recommendations

• A performance study on a single processing node of the HITACHI SR8000
• Performance evaluation of the Hitachi SR8000 using SPEC OMP2001 benchmarks
• Automatic intra-register vectorization for the Intel\(^\circledR\) architecture
• Code optimization techniques of data-intensive tasks onto statically scheduled architectures: Optimal performance on the TigerSharc
• scientific article; zbMATH DE number 4072349

Cited in

(1)

• Optimizing pipeline for a RISC processor with multimedia extension ISA

This page was built for publication: Pseudo-vectorization and RISC optimization techniques for the Hitachi SR8000 architecture

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4429610)