High level synthesis of integrated heterogeneous pipelined processing elements for DSP applications

DOI10.1016/J.COMPELECENG.2004.11.005MaRDI QIDQ2498249zbMATH OpenOpenAlexFDO

Authors Yanyan Li

Publication date 15 August 2006

Published in Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.compeleceng.2004.11.005

zbMATH Keywords

dataflow graphsheterogeneous multiprocessingprocessor assignmentrate-optimal schedulingstatic scheduling

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Recommendations

• Synthesis of resources sharing
• A unified approach for scheduling and allocation
• Optimal Scheduling of Digital Signal Processing Data-flow Graphs using Shortest-path Algorithms
• scientific article; zbMATH DE number 1041833
• scientific article; zbMATH DE number 53629

Cited in

(5)

• SOS: Synthesis of application-specific heterogeneous multiprocessor systems
• Resynchronization for multiprocessor DSP systems
• A unified approach for scheduling and allocation
• scientific article; zbMATH DE number 1041833 (Why is no real title available?)
• Synthesis of resources sharing

This page was built for publication: High level synthesis of integrated heterogeneous pipelined processing elements for DSP applications

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2498249)