Towards designing quantum reversible ternary multipliers
From MaRDI portal
Publication:2690519
Recommendations
- Design of a novel quantum reversible ternary up-counter
- Towards quantum reversible ternary coded decimal adder
- Design of quantum cost efficient reversible multiplier using Reed-Muller expressions
- A new design of a low-power reversible vedic multiplier
- An efficient design for reversible Wallace unsigned multiplier
Cites work
Cited in
(11)- Towards quantum reversible ternary coded decimal adder
- Designing novel quaternary quantum reversible subtractor circuits
- Novel qutrit circuit design for multiplexer, de-multiplexer, and decoder
- Design of quantum cost efficient reversible multiplier using Reed-Muller expressions
- Quantum reversible circuits for \(\mathrm{GF}(2^8)\) multiplication based on composite field arithmetic operations
- Design of a novel quantum reversible ternary up-counter
- Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate
- A new design of a low-power reversible vedic multiplier
- A fault-tolerant and scalable column-wise reversible quantum multiplier with a reduced size
- Designs of four universal architectures for multi-valued quantum adders
- Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer
This page was built for publication: Towards designing quantum reversible ternary multipliers
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2690519)