A fault-tolerant and scalable column-wise reversible quantum multiplier with a reduced size
From MaRDI portal
Publication:6043556
DOI10.1007/s11128-023-03857-xMaRDI QIDQ6043556
Shahram Etemadi Borujeni, Seyed Mansour Shahidi
Publication date: 23 May 2023
Published in: Quantum Information Processing (Search for Journal in Brave)
Cites Work
- Optimization approaches for designing quantum reversible arithmetic logic unit
- Controlled gates for multi-level quantum computation
- Heuristic methods to use don't cares in automated design of reversible and quantum logic circuits
- On figures of merit in reversible and quantum logic designs
- Improving the quantum cost of reversible Boolean functions using reorder algorithm
- Optimized 4-bit quantum reversible arithmetic logic unit
- Decompositions of \(n\)-qubit Toffoli gates with linear circuit complexity
- Effective designs of reversible Vedic multiplier
- Cost-efficient design of a quantum multiplier-accumulator unit
- Mapping NCV Circuits to Optimized Clifford+T Circuits
- Quantum Computing for Computer Scientists
This page was built for publication: A fault-tolerant and scalable column-wise reversible quantum multiplier with a reduced size
