A fault-tolerant and scalable column-wise reversible quantum multiplier with a reduced size

DOI10.1007/S11128-023-03857-XMaRDI QIDQ6043556FDOQ6043556

Authors: Seyed Mansour Shahidi, Shahram Etemadi Borujeni 

Publication date: 23 May 2023

Published in: Quantum Information Processing (Search for Journal in Brave)

zbMATH Keywords

quantum computingreversible logicmultiplier circuitancilla inputgarbage output

Mathematics Subject Classification ID

Quantum computation (81P68)

Cites Work

• Optimization approaches for designing quantum reversible arithmetic logic unit
• On figures of merit in reversible and quantum logic designs
• Heuristic methods to use don't cares in automated design of reversible and quantum logic circuits
• Controlled gates for multi-level quantum computation
• Quantum Computing for Computer Scientists
• Improving the quantum cost of reversible Boolean functions using reorder algorithm
• Decompositions of \(n\)-qubit Toffoli gates with linear circuit complexity
• Cost-efficient design of a quantum multiplier-accumulator unit
• Optimized 4-bit quantum reversible arithmetic logic unit
• Mapping NCV Circuits to Optimized Clifford+T Circuits
• Effective designs of reversible Vedic multiplier

Cited In (2)

• A novel fault-tolerant quantum divider and its simulation
• Quantum reversible circuits for \(\mathrm{GF}(2^8)\) multiplication based on composite field arithmetic operations

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