A high-speed residue-to-binary converter for three-moduli (2ᵏ, 2ᵏ -1, 2ᵏ-1 -1) RNS and a scheme for its VLSI implementation

DOI10.1109/82.899659MaRDI QIDQ2732968zbMATH OpenOpenAlexFDO

Authors Wei Wang, M. N. S. Swamy, M. O. Ahmad, Yuke Wang

Publication date 2 December 2001

Published in IEEE Transactions on Circuits and Systems. II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/82.899659

zbMATH Keywords

digital signal processingVLSLI implementation

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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(12)

• High speed residue to binary converter for the new four-moduli set \(\{2^{2n},2^n+1,2^{n/2}+1,2^{n/2}-1\}\)
• An improved residue-to-binary converter
• Novel high-radix residue number system architectures
• Hierarchical residue number systems with small moduli and simple converters
• An efficient residue to binary converter design
• Fast base extension using a redundant modulus in RNS
• Design of residue generators and multioperand adders modulo 3 built of multioutput threshold circuits
• An Overflow-Free Residue Multiplier
• Efficient CRT-based residue-to-binary converter for the arbitrary moduli set
• A VLSI structure forX(modm) operation
• Novel RNS structures for the moduli set \((2^{n}-1, 2^{n}, 2^{n}+1)\) and their application to digital filter implementation
• An efficient RNS parity checker for moduli set \(\{2^n - 1, 2^n + 1, 2^{2n} + 1\}\) and its applications

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