Towards a unifying CSP approach to hierarchical verification of asynchronous hardware

zbMATH Open1272.68278MaRDI QIDQ2848424FDOQ2848424

Authors: Xu Wang, Marta Kwiatkowska, G. Theodoropoulos, Q. Zhang 

Publication date: 26 September 2013

Full work available at URL: http://www.sciencedirect.com/science/article/pii/S157106610500246X

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Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Cited In (6)

• Structure-based deadlock checking of asynchronous circuits
• Title not available (Why is that?)
• RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking
• Verification of building blocks for asynchronous circuits
• Translating FSP into LOTOS and networks of automata
• On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP

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