Towards a unifying CSP approach to hierarchical verification of asynchronous hardware

MaRDI QIDQ2848424zbMATH OpenFDO

Authors Xu Wang, Marta Kwiatkowska, G. Theodoropoulos, Q. Zhang

Publication date 26 September 2013

Full work available at URL http://www.sciencedirect.com/science/article/pii/S157106610500246X

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

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(6)

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• RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking
• Verification of building blocks for asynchronous circuits
• Translating FSP into LOTOS and networks of automata
• On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP

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