Verification of building blocks for asynchronous circuits

DOI10.4204/EPTCS.114.6MaRDI QIDQ6587253zbMATHFDO

Authors Freek Verbeek, Julien Schmaltz

Publication date 13 August 2024

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Formalization of mathematics in connection with theorem provers (68V20) Theorem proving (automated and interactive theorem provers, deduction, resolution, etc.) (68V15)

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Cites work

• Verifying deadlock-freedom of communication fabrics

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