Verification of building blocks for asynchronous circuits

DOI10.4204/EPTCS.114.6zbMATH Open1542.681MaRDI QIDQ6587253FDOQ6587253

Authors: Freek Verbeek, Julien Schmaltz 

Publication date: 13 August 2024

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Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Formalization of mathematics in connection with theorem provers (68V20) Theorem proving (automated and interactive theorem provers, deduction, resolution, etc.) (68V15)

Cites Work

• Verifying deadlock-freedom of communication fabrics

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