A Minimum Area VLSI Network for O(log n) Time Sorting

DOI10.1109/TC.1985.5009384MaRDI QIDQ3219772zbMATH OpenFDO

Authors Gianfranco Bilardi, F. P. Preparata

Publication date 1985

Published in IEEE Transactions on Computers (Search for Journal in Brave)

zbMATH Keywords

parallel computationoptimal algorithmscube-connected cyclesVLSI implementationhybrid architectureparallel sorting algorithmsarea-time performancebitonic mergingcombination sortingorthogonal trees

Mathematics Subject Classification ID

Searching and sorting (68P10) Theory of operating systems (68N25)

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Cited in

(15)

• Area time trade-offs in micro-grain VLSI array architectures
• A VLSI partition algorithm
• Theoretical Aspects of VLSI Pin Limitations
• Systolic Sorting on a Mesh-Connected Network
• A unified \(O(\log N)\) and optimal sorting vector algorithm
• Parallel sorting in two-dimensional VLSI models of computation
• An Architecture for Bitonic Sorting with Optimal VLSI Performnance
• VLSI Sorting with Reduced Hardware
• Area-time lower-bound techniques with applications to sorting
• Minimum Storage Sorting Networks
• Optimal VLSI circuits for sorting
• scientific article; zbMATH DE number 3911723 (Why is no real title available?)
• Systolic sorting in a sequential input/output environment
• Area efficient layouts of the Batcher sorting networks
• VLSI-sorting evaluated under the linear model

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