Theoretical Aspects of VLSI Pin Limitations

DOI10.1137/0222027zbMATH Open0770.68080OpenAlexW2007200565MaRDI QIDQ4032944FDOQ4032944

Authors: Robert Cypher 

Publication date: 17 May 1993

Published in: SIAM Journal on Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1137/0222027

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zbMATH Keywords

parallel sortingVLSI theorypin limitations

Mathematics Subject Classification ID

Searching and sorting (68P10) Network design and communication in computer systems (68M10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (6)

• Minimum linear gossip graphs and maximal linear \((\Delta,k)\)-gossip graphs
• Deterministic sorting in nearly logarithmic time on the hypercube and related computers
• Broadcasting in a hypercube when some calls fail
• A lower bound for sorting networks based on the shuffle permutation
• A super-logarithmic lower bound for hypercubic sorting networks
• On \(k\)-partitioning the \(n\)-cube

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