Parallel Binary Adders with a Minimum Number of Connections

DOI10.1109/TC.1983.1676144MaRDI QIDQ3318686zbMATHOpenAlexFDO

Authors Akito Sakurai, Saburo Muroga

Publication date 1983

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1983.1676144

zbMATH Keywords

logic designminimal addern-bit parallel binary adderNOR gatesripple addersingle-rail input logic

Mathematics Subject Classification ID

Recommendations

• scientific article; zbMATH DE number 3873237
• Parallel multipliers with NOR gates based on G-minimum adders
• Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
• Binary adder circuits of asymptotically minimum depth, linear size, and fan-out two
• Publication:3033322

Cited in

(6)

• scientific article; zbMATH DE number 3873237 (Why is no real title available?)
• scientific article; zbMATH DE number 1304542 (Why is no real title available?)
• Minimal digit sets for parallel addition in non-standard numeration systems
• Two operand binary adders with threshold logic
• Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
• Parallel multipliers with NOR gates based on G-minimum adders

This page was built for publication: Parallel Binary Adders with a Minimum Number of Connections

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3318686)