Temporal Logic Verification Using Simulation
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Publication:3511234
DOI10.1007/11867340_13zbMATH Open1141.68463OpenAlexW2120953717MaRDI QIDQ3511234FDOQ3511234
Authors: Georgios E. Fainekos, Antoine Girard, George Pappas 
Publication date: 8 July 2008
Published in: Lecture Notes in Computer Science (Search for Journal in Brave)
Full work available at URL: https://repository.upenn.edu/cgi/viewcontent.cgi?article=1296&context=cis_papers
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Specification and verification (program logics, model checking, etc.) (68Q60) Temporal logic (03B44)
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- Monitoring bounded LTL properties using interval analysis
- Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces
- Robust satisfaction of temporal logic over real-valued signals
- Title not available (Why is that?)
- A survey of challenges for runtime verification from advanced application domains (beyond software)
- Temporal logic verification for delay differential equations
- Verification of Hybrid Systems
- Robustness of temporal logic specifications for continuous-time signals
- Sampling polynomial trajectories for LTL verification
- Approximate bisimulation: a bridge between computer science and control theory
- Temporal Logic Verification of Lock-Freedom
- Analog property checkers: a DDR2 case study
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