Temporal Logic Verification Using Simulation

DOI10.1007/11867340_13MaRDI QIDQ3511234zbMATH OpenOpenAlexFDO

Authors Georgios E. Fainekos, Antoine Girard, George Pappas

Publication date 8 July 2008

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://repository.upenn.edu/cgi/viewcontent.cgi?article=1296&context=cis_papers

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Temporal logic (03B44)

Recommendations

• Robust satisfaction of temporal logic over real-valued signals
• Hybrid Systems: Computation and Control
• Robustness of temporal logic specifications for continuous-time signals
• Focusing qualitative simulation using temporal logic: Theoretical foundations
• STL model checking of continuous and hybrid systems

Cited in

(12)

• Monitoring bounded LTL properties using interval analysis
• Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces
• Robust satisfaction of temporal logic over real-valued signals
• scientific article; zbMATH DE number 5368984 (Why is no real title available?)
• A survey of challenges for runtime verification from advanced application domains (beyond software)
• Temporal logic verification for delay differential equations
• Robustness of temporal logic specifications for continuous-time signals
• Verification of Hybrid Systems
• Sampling polynomial trajectories for LTL verification
• Approximate bisimulation: a bridge between computer science and control theory
• Temporal Logic Verification of Lock-Freedom
• Analog property checkers: a DDR2 case study

Describes a project that uses

Uses Software

• PHAVer

This page was built for publication: Temporal Logic Verification Using Simulation

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3511234)