An analytical model for Network-on-Chip with finite input buffer

DOI10.1007/S11704-010-0117-0zbMATH Open1267.68075OpenAlexW1993298594MaRDI QIDQ352048FDOQ352048

Authors: Yu-Bai Li, Chang Wu, Jian Wang 

Publication date: 4 July 2013

Published in: Frontiers of Computer Science in China (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11704-010-0117-0

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zbMATH Keywords

finite bufferanalytical modelNetwork-on-Chip (NoC)queue system

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

Cites Work

• Title not available (Why is that?)
• Network calculus. A theory of deterministic queueing systems for the Internet
• Title not available (Why is that?)
• Analysis of a tandem network model of a single-router network-on-chip

Cited In (4)

• Buffer planning for application-specific networks-on-chip design
• Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays
• Analysis of the input to a buffer storage in front of a packet switch
• Analysis of a tandem network model of a single-router network-on-chip

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