On retiming for FPGA logic module minimization

DOI10.1016/S0167-9260(97)00029-1MaRDI QIDQ4224366zbMATH OpenFDO

Authors

Publication date 12 January 1999

Published in Integration (Search for Journal in Brave)

zbMATH Keywords

FPGAlinear programretiminglogic module

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

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Cited in

(2)

• Minimization of circuit registers: Retiming revisited
• In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults

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