scientific article; zbMATH DE number 1941116

MaRDI QIDQ4408166zbMATH OpenFDO

Authors Eric Roesler, Brent Nelson

Publication date 29 June 2003

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2438/24380637.htm

Mathematics Subject Classification ID

Computing methodologies and applications (68U99)

Recommendations

• Implementation of floating point arithmetics using an FPGA
• Series expansion based efficient architectures for double precision floating point division
• Performance evaluation and optimal design for FPGA-based digit-serial DSP functions
• Multiple constant multiplication optimizations for field programmable gate arrays. With a preface by Prof. Dr.-Ing. Peter Zipf
• FPGA based high performance double-precision matrix multiplication

Cited in

(9)

• scientific article; zbMATH DE number 1941118 (Why is no real title available?)
• Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support
• Performance evaluation and optimal design for FPGA-based digit-serial DSP functions
• A low power approach to floating point adder design for DSP application
• Series expansion based efficient architectures for double precision floating point division
• On the design of IEEE compliant floating point units
• Implementation of floating point arithmetics using an FPGA
• Energy-Efficient Floating-Point Unit Design
• scientific article; zbMATH DE number 1941105 (Why is no real title available?)

This page was built for publication:

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4408166)