Series expansion based efficient architectures for double precision floating point division

DOI10.1007/S00034-014-9811-8zbMATH Open1342.68030OpenAlexW1972471256MaRDI QIDQ736327FDOQ736327

Authors: D. Kharzeev 

Publication date: 3 August 2016

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: http://hdl.handle.net/10722/247396

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zbMATH Keywords

divisionaccuracyarithmeticTaylor series expansionFPGAKaratsuba methodfloating point arithmeticpartial block multiplication

Mathematics Subject Classification ID

Series expansions (e.g., Taylor, Lidstone series, but not Fourier series) (41A58) Mathematical problems of computer architecture (68M07) Numerical algorithms for computer arithmetic, etc. (65Y04)

Cites Work

• Division unit with Newton-Raphson approximation and digit-by-digit refinement of the quotient
• FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture
• The IBM System/360 Model 91: Floating-Point Execution Unit

Cited In (2)

• Implementation of floating point arithmetics using an FPGA
• Title not available (Why is that?)

Uses Software

• VFloat

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