scientific article; zbMATH DE number 2019777

MaRDI QIDQ4440472zbMATH OpenFDO

Authors Mohab Anis, Mohamed I. Elmasry

Publication date 18 December 2003

zbMATH Keywords

CMOSdigital circuitsleakage powerVLSI design

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Introductory exposition (textbooks, tutorial papers, etc.) pertaining to information and communication theory (94-01) Analytic circuit theory (94C05)

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Cited in

(4)

• Modeling leakage power reduction in VLSI as optimization problems
• Low power high-speed multithreshold voltage CMOS bus architectures
• Design of CMOS low-power pre-settable edge-triggered flip-flop based on multithreshold technique
• An innovative power-gating technique for leakage and ground bounce control in system-on-a-chip (SOC)

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