Delay and noise estimation of CMOS logic gates driving coupled resistive–capacitive interconnections

DOI10.1016/S0167-9260(00)00005-5MaRDI QIDQ4520151zbMATH OpenFDO

Authors Ketan Tang, Eby G. Friedman

Publication date 12 December 2000

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/S0167-9260(00)00005-5

zbMATH Keywords

CMOS integrated circuitscoupling noisedeep submicrometerdelay uncertaintyinterconnectsignal activityVLSI

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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Cited in

(3)

• Modelling of source-coupled logic gates
• Power-delay optimization of D-latch/MUX source coupled logic gates
• FET-R-C Circuits: A Unified Treatment—Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance

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