Optimizing pairwise box intersection checking on GPUs for large-scale simulations

DOI10.1145/2499913.2499918zbMATH Open1390.65201OpenAlexW2021332852MaRDI QIDQ4635224FDOQ4635224

Authors: Shih-Hsiang Lo, I-Hsin Chung, Yeh-Ching Chung, Che-Rung Lee 

Publication date: 16 April 2018

Published in: ACM Transactions on Modeling and Computer Simulation (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1145/2499913.2499918

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zbMATH Keywords

data compressionload-balancingbox intersection checkingpipelined execution

Mathematics Subject Classification ID

Parallel numerical computation (65Y05) Computer graphics; computational geometry (digital and algorithmic aspects) (68U05) Coding and information theory (compaction, compression, models of communication, encoding schemes, etc.) (aspects in computer science) (68P30)

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