Reducing the use of resources in the FPGA circuit of a Moore FSM

DOI10.1007/S10559-013-9586-0zbMATH Open1316.94134OpenAlexW2018313747MaRDI QIDQ466444FDOQ466444

Authors: L. A. Tytarenko, R. V. Malcheva, K. A. Soldatov, Alexander Barkalov 

Publication date: 27 October 2014

Published in: Cybernetics and Systems Analysis (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10559-013-9586-0

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zbMATH Keywords

FPGAflowgraph of an algorithmMoore finite-state machinepseudoequivalent state

Mathematics Subject Classification ID

Formal languages and automata (68Q45)

Cites Work

• Title not available (Why is that?)
• Logic synthesis for compositional microprogram control units
• Principles of logic optimization for a Moore microprogrammed automaton

Cited In (4)

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• Title not available (Why is that?)
• Hardware reduction for LUT-based Mealy FSMs
• Title not available (Why is that?)

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